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E2L0044-17-Y1
Semiconductor MSM548512L
Semiconductor 524,288-Word 8-Bit High-Speed PSRAM
This version: Jan. 1998 MSM548512L Previous version: Dec. 1996
DESCRIPTION
The MSM548512L is fabricated using OKI's CMOS silicon gate process technology. This process, coupled with single-transister memory storage cells, permits maximum circuit density, minimum chip size and high speed. MSM548512L has Self-refresh mode in addition to Address-refresh mode and Auto-refresh mode. In the Self-refresh mode the internal refresh timer and address counter refresh the dynamic memory cells automatically. This series allows low power consumption when using standby mode with Self-refresh. The MSM548512L also features a static RAM-like write function that writes the data into the memory cell at the rising edge of WE.
FEATURES
* Large capacity * Fast access time * Low power * Refresh free * Logic compatible * Single power supply * Refresh * Package compatible * Package options: 32-pin 600 mil plastic DIP 32-pin 525 mil plastic SOP : : : : : : : : 4-Mbit (524,288-word 8 bits) 80 ns max. 200 A max. (standby with Self-refresh) Self refresh SRAM WE pin, no address multiplex 5 V 10% 2048 cycle/32 ms auto-address refresh SRAM standard package
(DIP32-P-600-2.54) (Product : MSM548512L-xxRS) (SOP32-P-525-1.27-K) (Product : MSM548512L-xxGS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM548512L-80RS MSM548512L-10RS MSM548512L-12RS MSM548512L-80GS-K MSM548512L-10GS-K MSM548512L-12GS-K Access Time (Max.) 80 ns 100 ns 120 ns 80 ns 100 ns 120 ns 525 mil 32-pin Plastic SOP 600 mil 32-pin Plastic DIP Package
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Semiconductor
MSM548512L
PIN CONFIGURATION (TOP VIEW)
A18 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 VSS 16 32-Pin Plastic DIP
32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE/RFSH 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
A18 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8
A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 VSS 16
,
32-Pin Plastic SOP
32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE/RFSH 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
Pin Name A0 - A18 I/O0 - I/O7 CE OE/RFSH WE VCC VSS
Function Address Input Data Input/Output Chip Enable Input Output Enable / Refresh Input Write Enable Input Power Voltage (5 V) Ground (0 V)
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Semiconductor
MSM548512L
BLOCK DIAGRAM
A0
Address Latch Control A10
Row Decoder
Memory Matrix (2048 256) 8
I/O0 Input Data Control
Column I/O Column Decoder
I/O7
Address Latch Control
A11
A18
Refresh Control
CE Timing Pulse Generator OE/RFSH WE Read/Write Control
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Semiconductor
MSM548512L
FUNCTION TABLE
CE L L L H H OE/RFSH L X H L H WE H L H X X I/O Pin Low-Z High-Z High-Z High-Z High-Z Mode Read Write -- Refresh Standby
L : Low Level Input H : High Level Input X : Don't Care
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin from VSS *1 Power Dissipation Operating Temperature Storage Temperature Storage Temperature (biased) Short Circuit Output Current Symbol VT PD Topr Tstg Tbias IOS Rating -1.0 to 7.0 1.0 0 to 70 -55 to 125 -10 to 85 50 Unit V W C C C mA
*1 Note:
To VSS 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(Ta = 0C to 70C) Min. 4.5 0 2.4 -0.5 Typ. 5.0 0 -- -- Max. 5.5 0 6.0 0.8 Unit V V V V
Recommended Operating Conditions
Parameter Power Supply Voltage Input Voltage Symbol VCC VSS VIH VIL
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Semiconductor
MSM548512L
DC Characteristics
Parameter Operating Current Symbol ICC1 ISB1 Standby Current ISB2 ICC2 Self Refresh Current ICC3 Input Leakage Current Output Leakage Current Output Low Level Output High Level ILI ILO VOL VOH -- -10 -10 -- 2.4 100 -- -- -- -- 200 10 10 0.4 -- -- -- 100 1 200 2 Min. -- -- Typ. 50 1 Max. 75 2
(VCC = 5 V 10%, VSS = 0 V, Ta = 0C to 70C) Unit mA mA mA mA mA mA mA V V Condition II/O = Open, tcyc = min. CE = VIH, OE/RFSH = VIH, VIN 0 V CE VCC - 0.2 V, VIN 0 V, OE/RFSH VCC - 0.2 V CE = VIH, OE/RFSH = VIL, VIN 0 V CE VCC - 0.2 V, VIN 0 V, OE/RFSH 0.2 V VCC = 5.5 V, VIN = VSS to VCC OE/RFSH = VIH, VI/O = VSS to VCC IOL = 2.1 mA IOH = -1 mA
Capacitance
Parameter Input Capacitance I/O Pin Capacitance Symbol CIN CI/O Condition VIN = 0 V VI/O = 0 V Min. -- -- Typ. -- -- Max. 8 10 Unit pF pF
Note:
This parameter is periodically sampled and is not 100% tested.
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Semiconductor
MSM548512L
AC Characteristics Measurement condition:
Input pulse level ........................... VIH = 2.4 V, VIL = 0.4 V Output reference level .................. VOH = 2.0 V, VOL = 0.8 V Rising and falling time ................. 5 ns Output load .................................... 1 TTL + 100 pF Input timing reference level ........ High = 2.2 V, Low = 0.8 V
(VCC = 5 V 10%, Ta = 0C to 70C) MSM548512L MSM548512L MSM548512L -80 -10 -12 Symbol Unit Note Min. Max. -- -- 80 30 25 -- 25 -- 10m -- -- -- -- -- -- -- -- -- -- -- -- 20 50 -- -- 8m -- -- -- 32 Min. 180 240 -- -- -- 20 -- 0 100n 70 0 25 0 0 15 0 30 100 25 0 5 -- 3 70 40 80n 180 8 600 -- Max. -- -- 100 30 30 -- 25 -- 10m -- -- -- -- -- -- -- -- -- -- -- -- 25 50 -- -- 8m -- -- -- 32 Min. 210 280 -- -- -- 20 -- 0 120n 80 0 30 0 0 15 0 35 120 30 0 5 -- 3 80 40 80n 210 8 600 -- Max. -- -- 120 50 30 -- 30 -- 10m -- -- -- -- -- -- -- -- -- -- -- -- 30 50 -- -- 8m -- -- -- 32 ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ms ns ms 6 11 6 6 tRC tRWC tCEA tOEA tCHZ tCLZ tOHZ tOLZ tCE tP tAS tAH tRCS tRCH tOHC tOCD tWP tCW tDW tDH tOW tWHZ tT tRFD tFP tFAP tFC tFAS tRFS tREF 160 220 -- -- -- 20 -- 0 80n 70 0 20 0 0 15 0 25 80 20 0 5 -- 3 70 40 80n 160 8 600 --
Parameter Random Read Write Cycle Time Random Read Modify Write Cycle Time CE Access Time OE Access Time Chip Disable to Output in High-Z CE to Output in Low-Z OE Disable to Output in High-Z OE Output in Low-Z CE Pulse Width CE Precharge Time Address Set-up Time Address Hold Time Read Command Set-up Time Read Command Hold Time OE Command Hold Time OE Delay Time Write Command Pulse Width Chip Enable Time Input Data Set Time Input Data Hold Time Output Active from End of Write Write Enable to Output in High-Z Transition Time RFSH Delay Time from CE RFSH Precharge Time RFSH Pulse Width (Auto-refresh) Auto-refresh Cycle Time RFSH Pulse Width (Self-refresh) CE Delay Time from RFSH in Self-refresh Mode Refresh Period (2048 cycle/32 ms)
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Semiconductor Notes:
MSM548512L
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to ground. 3. ICC1 depends on output loading. Specified values are obtained with the output open. 4. An initial pause of 100 s is required after power-up followed by more than 8 initial cycles before proper device operation is achieved. 5. AC measurements assume tT = 5 ns. 6. tCHZ, tWHZ and tOHZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. In write cycles, the input data is latched at the earlier rising point of either CE or WE. Write operation is achieved when both CE and WE are low. 8. The I/O state remains at high impedance after CE goes low if the transition occurs at the same time as or after the falling edge of WE. 9. Use WE or OE or both signals to disable the output before input data is applied during a write cycle when the input is not the same. 10. Data input must be set to floating state before I/O becomes low impedance by WE or OE or both. 11. VIH (Min.) and VIL (Max.) are input timing reference levels for measurement. The transition time is measured between VIL and VIH. 12. 2048-cycle refresh must be applied within 15 s after the end of self refreshing to satisfy 2048 cycles/32 ms.
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, ,,, ,,,
TIMING WAVEFORM
Read Cycle
tRC CE tCE tP tAS tAH Address A0 - A18 WE tRCS tRCH tCEA tOHC OE/RSFH tOEA tOLZ tOHZ tCHZ DOUT Valid Data-out "H" or "L"
Semiconductor
MSM548512L
Write Cycle 1 (OE High)
tRC
CE
tCE
tP
tAS
tAH
Address A0 - A18 WE
tCW
tWP
OE/RFSH
tOCD
tDW
tDH
DIN
tWHZ
Valid Data-in
tOLZ
tCLZ DOUT
tOHZ
tCHZ
tOW
"H" or "L"
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Semiconductor
Write Cycle 2 (OE Low)
CE
Read Modify Write
,,, , , ,,,
MSM548512L
tRC tCE tP tAS tAH Address A0 - A18 WE tCW tOHC tWP OE/RFSH tDW tDH DIN tCLZ tWHZ Valid Data-in DOUT "H" or "L"
tRWC
CE
tP
tAS
tAH
Address A0 - A18 WE
tRCS
tCW
tRCH
tWP
tOHC
tOCD
OE/RFSH
tOHZ
tOEA
tDW
tDH
DIN tCLZ DOUT
tOLZ
Valid Data-in tWHZ
Valid Data-out
tCHZ tOW
"H" or "L"
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, , , ,
Semiconductor MSM548512L Auto Refresh Cycle
CE tRFD tFC tFC tFP tFAP tFP tFAP OE/RFSH "H" or "L"
Self Refresh Cycle
CE
tRFD
tFP
tFAS
tRFS
OE/RFSH
"H" or "L"
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Semiconductor
MSM548512L
PACKAGE DIMENSIONS
(Unit : mm)
DIP32-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 4.70 TYP.
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Semiconductor
MSM548512L
(Unit : mm)
SOP32-P-525-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.32 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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